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19-0147; Rev. 4; 11/05
Microprocessor and Nonvolatile Memory Supervisory Circuits
General Description
The MAX792/MAX820 microprocessor (P) supervisory circuits provide the most functions for power-supply and watchdog monitoring in systems without battery backup. Built-in features include the following: * P reset: Assertion of RESET and RESET outputs during power-up, power-down, and brownout conditions. RESET is guaranteed valid for VCC down to 1V. * Manual-reset input. * Two-stage power-fail warning: A separate low-line comparator compares V CC to a preset threshold 120mV above the reset threshold; the low-line and reset thresholds can be programmed externally. * Watchdog fault output: Assertion of WDO if the watchdog input is not toggled within a preset timeout period. * Pulsed watchdog output: Advance warning of impending WDO assertion from watchdog timeout that causes hardware shutdown. * Write protection of CMOS RAM, EEPROM, or other memory devices. The MAX792 and MAX820 are identical, except the MAX820 guarantees higher low-line and reset threshold accuracy (2%).
Features
Manual-Reset Input 200ms Power-OK / Reset Time Delay Independent Watchdog Timer--Preset or Adjustable On-Board Gating of Chip-Enable Signals Memory Write-Cycle Completion 10ns (max) Chip-Enable Gate Propagation Delay Voltage Monitor for Overvoltage Warning 2% Reset and Low-Line Threshold Accuracy (MAX820, external programming mode)
MAX792/MAX820
Ordering Information
PART** MAX792_CPE MAX792_CSE MAX792_C/D TEMP. RANGE 0C to +70C 0C to +70C 0C to +70C PIN-PACKAGE 16 Plastic DIP 16 Narrow SO Dice*
Ordering Information continued at end of data sheet.
* Dice are tested at TA = +25C, DC parameters only. **These parts offer a choice of five different reset threshold voltages. Select the letter corresponding to the desired nominal reset threshold voltage and insert it into the blank to complete the part number. Devices in PDIP, SO and MAX packages are available in both leaded and lead-free packaging. Specify lead free by adding the + symbol at the end of the part number when ordering. Lead free not available for CERDIP package.
Applications
Computers Controllers Intelligent Instruments Critical P Power Monitoring
SUFFIX L M T S R
RESET THRESHOLD (V) 4.62 4.37 3.06 2.91 2.61
Typical Operating Circuit
3 VCC 4 CE OUT RESET IN/INT 0.1F 13 VCC
VCC
P MAX792
5 LLIN/ REFOUT CE IN OVO LOW LINE 7 8 OVI SWT GND 12 RESET MR 14 6 10 1 9 GND NMI RESET ADDRESS DECODER RAM A0-A15
________________________________________________________________ Maxim Integrated Products
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Microprocessor and Nonvolatile Memory Supervisory Circuits MAX792/MAX820
ABSOLUTE MAXIMUM RATINGS
Input Voltage (with respect to GND) VCC .......................................................................-0.3V to +6V All Other Inputs.......................................-0.3V to (VCC + 0.3V) Input Current GND ................................................................................25mA All Other Outputs ............................................................25mA Continuous Power Dissipation (TA = +70C) Plastic DIP (derate 10.53mW/C above +70C) ..........842mW Narrow SO (derate 9.52mW/C above +70C) ............762mW CERDIP (derate 10.00mW/C above +70C) ...............800mW Operating Temperature Ranges: MAX792_C_ _/MAX820_C_ _ ...............................0C to +70C MAX792_E_ _/MAX820_E_ _.............................-40C to +85C MAX792_MJE_ _/MAX820_MJE_ _ .................-55C to +125C Storage Temperature Range .............................-65C to +160C Lead Temperature (soldering, 10s) .................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VCC = 2.75V to 5.5V, TA = TMIN to TMAX, unless otherwise noted.) PARAMETER Operating Voltage Range (Note 1) Supply Current RESET COMPARATOR MAX792L, MAX820L MAX792M, MAX820M MAX792R, MAX820R MAX792S, MAX820S Reset Threshold Voltage-- Internal Threshold Mode (VTH) MAX792T, MAX820T MAX820L, TA = +25C, VCC falling MAX820M, TA = +25C, VCC falling MAX820R, TA = +25C, VCC falling MAX820S, TA = +25C, VCC falling MAX820T, TA = +25C, VCC falling MAX792, VCC = 5V or VCC = 3V MAX820, VCC = 5V or VCC = 3V Internal threshold mode 0.01 VCC falling VCC rising ISINK = 50A, VCC = 1V, VCC falling ISINK = 1.6mA ISOURCE = 1mA ISOURCE = 100A ISINK = 1.6mA ISOURCE = 1mA ISOURCE = 100A 4.50 4.25 2.55 2.85 3.00 4.55 4.30 2.55 2.85 3.00 1.25 1.274 4.62 4.37 2.61 2.91 3.06 4.75 4.50 2.70 3.00 3.15 4.70 4.45 2.66 2.96 3.11 1.35 1.326 60 25 V CONDITIONS MIN 2.75 70 150 TYP MAX UNITS V A
Reset Threshold Voltage External Threshold Mode (VTH) RESET IN/INT Mode Threshold (Note 2) RESET IN/INT Leakage Current Reset Threshold Hysteresis Reset Comparator Delay Reset Active Timeout Period
1.30 1.30
V mV nA V s ms
140
RESET Output Voltage
0.016 x VTH 70 200 280 0.01 0.3 0.1 0.4
VCC - 1 VCC - 0.5 0.1 VCC - 1 VCC - 0.5 0.4
V
RESET Output Voltage
V
2
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Microprocessor and Nonvolatile Memory Supervisory Circuits
ELECTRICAL CHARACTERISTICS (continued)
(VCC = 2.75V to 5.5V, TA = TMIN to TMAX, unless otherwise noted.) PARAMETER LOW-LINE COMPARATOR Low-Line Threshold Voltage (Internal Threshold Mode)--VTH Low-Line Threshold Voltage (External Programming Mode) Low-Line Hysteresis (Internal Threshold Mode) LLIN/REFOUT Leakage Current External Programming Mode Low-Line Comparator Delay LOWLINE Voltage LOWLINE Short-Circuit Current WATCHDOG FUNCTION SWT connected to VCC, VCC = 5V SWT connected to VCC, VCC = 3V Watchdog Timeout Period 4.7nF capacitor connected from SWT to GND, VCC = 3V 4.7nF capacitor connected from SWT to GND, VCC = 5V Watchdog Input Pulse Width VCC = 5V VCC = 3V ISINK = 50A, VCC = 1V, VCC falling ISINK = 1.6mA ISOURCE = 1mA ISOURCE = 100A VIL = 0V, VIH = VCC 100 300 0.01 0.1 VCC - 1 VCC - 0.5 70 0.5 ISINK = 50A, VCC = 1V, VCC falling ISINK = 1.6mA ISOURCE = 1mA ISOURCE = 100A VIH VCC = 4.25V VIL VIH VCC = 2.55V VIL 1.7 0.01 0.1 VCC - 1 VCC - 0.5 0.75 x VCC 0.8 0.9 x VCC 0.2 1 6.0 0.3 0.4 0.30 0.4 1.00 1.00 1.60 1.60 70 ms 100 ns 2.25 2.25 sec VCC falling ISINK = 3.2mA
ISOURCE = 1A
MAX792/MAX820
CONDITIONS MAX792/MAX820L/M MAX792/MAX820R/S/T MAX792, VCC = 5V OR VCC = 3V MAX820, VCC = 5V OR VCC = 3V
MIN 50 40 1.25 1.274
TYP 120 100 1.30 1.30 20 0.01 450
MAX 210 210 1.35 1.326
UNITS
mV V mV
25
nA s
0.4 VCC - 1 10 50
V A
Output source current, VCC = 5.5V
WDO Output Voltage
V
WDPO to WDO Delay WDPO Duration
ns ms
WDPO Output Voltage
V
WDI Threshold Voltage
V
WDI Input Current
A
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Microprocessor and Nonvolatile Memory Supervisory Circuits MAX792/MAX820
ELECTRICAL CHARACTERISTICS (continued)
(VCC = +2.75V to +5.5V, TA = TMIN to TMAX, unless otherwise noted.) PARAMETER OVERVOLTAGE COMPARATOR OVI Input Threshold OVI Leakage Current OVO Output Voltage OVO Short-Circuit Current OVI to OVO Delay CHIP-ENABLE GATING VCC = 4.25V CE IN Threshold Voltage VCC = 2.55V CE IN Leakage Current CE IN to CE OUT Resistance CE OUT Short-Circuit Current Chip-Enable Propagation Delay (Note 3) Chip-Enable Output Voltage High (Reset Active) Reset Active to CE OUT High MANUAL RESET MR Minimum Pulse Width MR to RESET Propagation Delay MR Threshold Range MR Pull-Up Current MR = 0V VCC = 4.25V to VCC = 5.5V VCC = 2.5V 1.1 5 1 25 12 1.3 23 1.5 80 s s V A Disabled mode Enabled mode Disabled mode, CEOUT = 0V 50 source impedance driver, CLOAD = 50pF IOUT = -100A IOUT = 10A VCC falling VCC = 5V VCC = 3V VCC = 5V VCC = 3V VCC = 5V VCC = 3V VCC - 1 VCC - 0.5 15 VIH VIL VIH VIL 0.75 x VCC 0.8 0.75 x VCC 0.2 0.005 75 150 0.5 0.05 0.2 6 8 1 150 300 2.5 0.4 10 13 A mA ns V s V ISINK = 3.2mA ISOURCE = 1A Output source current, VCC = 5.5V VOD = 100mV, OVI rising VOD = 100mV, OVI falling VCC - 1 10 13 55 50 VCC = 5V or VCC = 3V 1.25 1.30 0.01 1.35 25 0.4 V nA V A s CONDITIONS MIN TYP MAX UNITS
Note 1: The minimum operating voltage is 2.75V; however, the MAX792R and MAX820R are guaranteed to operate down to their preset reset thresholds. Note 2: Pulling RESET IN/INT below 60mV selects internal threshold mode and connects the internal voltage divider to the reset and low-line comparators. External programming mode allows an external resistor divider to set the low-line and reset thresholds (see Figure 4). Note 3: The Chip-Enable Propagation delay is measured from the 50% point at CE IN to the 50% point at CE OUT.
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Microprocessor and Nonvolatile Memory Supervisory Circuits MAX792/MAX820
__________________________________________Typical Operating Characteristics
(TA = +25C, unless otherwise noted.)
SUPPLY CURRENT vs. TEMPERATURE
MAX792-1
OVERVOLTAGE COMPARATOR PROPAGATION DELAY vs. TEMPERATURE
MAX792-2
RESET COMPARATOR PROPAGATION DELAY vs. TEMPERATURE
MAX792-3
100 90 80 SUPPLY CURRENT (A) 70 60 50 40 30 20 10 0 -60 -30 0 30 60 90 120 VCC = 2V VCC = 4V VCC = 3V VCC = 5V SWT = VCC ALL OUTPUTS UNLOADED
70
80
PROPAGATION DELAY (s)
PROPAGATION DELAY (s) VIH TO VOL VIN = 20mV OVERDRIVE = 15mV
60
70
50
60
40
50 VCC FALLING 15mV OVERDRIVE EXTERNAL PROGRAMMING MODE -60 -30 0 30 60 90 120 150
30 150 -60 -30 0 30 60 90 120 150 TEMPERATURE (C) TEMPERATURE (C)
40
TEMPERATURE (C)
LOW-LINE COMPARATOR PROPAGATION DELAY vs. TEMPERATURE
MAX792-3a
POWER-UP RESET DELAY vs. TEMPERATURE
MAX792-4
NOMINAL WATCHDOG TIMEOUT PERIOD vs. VCC
NOMINAL WATCHDOG TIMEOUT PERIOD (s)
MAX792-5
600 500 VCC = 5V
300 250 200
3.0
PROPAGATION DELAY (s)
2.5
400
DELAY (ms)
150 100 50 0
2.0
300
VCC = 3V VCC FALLING 15mV OVERDRIVE EXTERNAL PROGRAMMING MODE -60 -30 0 30 60 90 120 150
200 100
1.5
1.0 -60 -30 0 30 60 90 120 150 2 3 VCC (V) 4 5 TEMPERATURE (C)
TEMPERATURE (C)
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Microprocessor and Nonvolatile Memory Supervisory Circuits MAX792/MAX820
Typical Operating Characteristics (continued)
(TA = +25C, unless otherwise noted.)
INTERNAL-MODE RESET THRESHOLD vs. TEMPERATURE (NORMALIZED)
MAX792-6
REF OUT VOLTAGE vs. TEMPERATURE
MAX792-7
CHIP-ENABLE ON-RESISTANCE vs. TEMPERATURE
180 160 ON-RESISTANCE () 140 120 100 80 60 40 VCC = 5V VCE IN = 2.5V VCC = 3V VCE IN = 1.5V
MAX792-8
1.125 1.100 1.075 RESET THRESHOLD 1.050 1.025 1.000 0.975 0.950 0.925 0.900 -60 THE RESET THRESHOLD IS SHOWN NORMALIZED TO 1, REPRESENTING ALL AVAILABLE MAX792/MAX820 -30 0 30 60 90 120
1.33 1.32 1.31 REF OUT (V) 1.30 1.29 1.28 1.27 1.26 1.25 RESET IN / INT = 0V -60 -30 0 30 60 90 120
200
20 0 150 -60 -30 0 30 60 90 120 150
150
TEMPERATURE (C)
TEMPERATURE (C)
TEMPERATURE (C)
WATCHDOG TIMEOUT PERIOD vs. SWT LOAD CAPACITANCE
MAX792-10
CHIP-ENABLE PROPAGATION DELAY vs. CE OUT LOAD CAPACITANCE
VCC = +5V VCE IN = 0V TO 5V DRIVER SOURCE IMPEDANCE = 50
MAX792-11
100k WATCHDOG TIMEOUT PERIOD (ms)
20
PROPAGATION DELAY (ns) 1m
10k
15
1k
VCC = 5V VCC = 3V
10
100
5
10 1n 10n CSWT (F) 100n
0 0 25 50 75 100 125 150 175 200 225 250 CLOAD (pF)
6
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Microprocessor and Nonvolatile Memory Supervisory Circuits
______________________________________________________________Pin Description
PIN NAME RESET FUNCTION Active-Low Reset Output goes low whenever VCC falls below the reset threshold in internal threshold programming mode, or RESET IN falls below 1.30V in external threshold programming mode. RESET remains low for 200ms typ after the threshold is exceeded on power-up. Reset is the inverse of RESET. Input Supply Voltage Reset-Input/Internal-Mode Select. Connect this input to GND to select internal threshold mode. Select external programming mode by pulling this input 600mV or higher through an external voltage divider. Low-Line Input/Reference Output connects directly to the low-line comparator in external programming mode (RESET IN/INT 600mV). Connects directly to the internal 1.30V reference in internal threshold mode (RESET IN/INT 60mV). Overvoltage Comparator Output goes low when OVI is greater than 1.30V. This is an uncommitted comparator and has no effect on any other internal circuitry. Inverting Input to the Overvoltage Comparator. When OVI is greater than 1.30V, OVO goes low. Connect OVI to GND or VCC when not used. Set Watchdog-Timeout Input. Connect this input to VCC to select the default 1.6sec watchdog timeout period. Connect a capacitor between this input and GND to select another watchdogtimeout period. Watchdog timeout period = k x (capacitor value in nF)mV, where k = 27 for VCC = 5V and k = 16.2 for VCC = 3V. If the watchdog function is unused, connect SWT to VCC. Manual-Reset Input. This input can be tied to an external momentary pushbutton switch, or to a logic gate output. Internally pulled up to VCC. Low-Line Output. LOW LINE goes low 120mV above the reset threshold in internal threshold mode, or when LLIN/REFOUT goes below 1.30V in external programming mode. Watchdog Input. If WDI remains either high or low for longer than the watchdog timeout period, WDPO pulses low and WDO goes low. WDO remains low until the next transition at WDI. Connect to GND or VCC if unused. Ground Chip-Enable Output. CE OUT goes low only when CE IN is low and reset is not asserted. If CE IN is low when reset is asserted, CE OUT will stay low for 15s or until CE IN goes high, whichever occurs first. Chip-Enable Input--the input to the chip-enable transmission gate. Connect to GND or VCC if not used. Watchdog Output. WDO goes low if WDI remains either high or low longer than the watchdog timeout period. WDO returns high on the next transition at WDI. Watchdog-Pulse Output. Upon the absence of a transition at WDI, WDPO will pulse low for a minimum of 500s. WDPO precedes WDO by typically 70ns.
MAX792/MAX820
1
2 3
RESET VCC RESET IN/INT
4
5
LLIN/REF OUT
6
OVO
7
OVI
8
SWT
9
MR
10
LOW LINE
11
WDI
12
GND
13
CE OUT
14
CE IN
15
WDO
16
WDPO
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Microprocessor and Nonvolatile Memory Supervisory Circuits MAX792/MAX820
Detailed Description
Manual-Reset Input
Many P-based products require manual-reset capability, allowing the operator to initiate a reset. The manual/external-reset input (MR) can connect directly to a switch without an external pull-up resistor or debouncing network. MR internally connects to a 1.30V comparator, and has a high-impedance pull-up to VCC, as shown in Figure 1. The propagation delay from asserting MR to reset asserted is typically 12s. Pulsing MR low for a minimum of 25s asserts the reset function (see Reset Function section). The reset output remains active as long as MR is held low, and the reset timeout period begins after MR returns high (Figure 2). To provide extra noise immunity in high-noise environments, pull MR up to VCC with a 100k resistor. Use MR as either a digital logic input or as a second lowline comparator. Normal TTL/CMOS levels can be wire-OR connected via pull-down diodes (Figure 3), and open-drain/collector outputs can be wire-ORed directly. External Programming Mode Connecting RESET IN/INT to a voltage above 600mV selects external programming mode. In this mode, the low-line and reset comparators disconnect from the internal voltage divider and connect to LLIN/REFOUT and RESET IN/INT, respectively (Figure 1). This mode allows flexibility in determining where in the operating voltage range the NMI and reset are generated. Set the low-line and reset thresholds with an external resistor divider, as in Figure 4b or Figure 4c. RESET typically remains valid for VCC down to 2.5V; RESET is guaranteed to be valid with VCC down to 1V. Calculate the values for the resistor voltage divider in Figure 4b using the following equations: 1) R3 = (1.30 x VCC MAX)/(VLOW LINE x IMAX) 2) R2 = [(1.30 x VCC MAX)/(VRESET x IMAX)] - R3 3) R1 = (VCC MAX/IMAX) - (R2 + R3). First choose the desired maximum current through the voltage divider (IMAX) when VCC is at its highest (VCC MAX). There are two things to consider here. First, IMAX contributes to the overall supply current for the circuit, so you would generally make it as small as possible. Second, IMAX cannot be too small or leakage currents will adversely affect the programmed threshold voltages; 5A is often appropriate. Determine R3 after you have chosen IMAX. Use the value for R3 to determine R2, then use both R2 and R3 to determine R1. For example, to program a 4.75V low-line threshold and a 4.4V reset threshold, first choose IMAX to be 5A when VCC = 5.5V and substitute into equation 1. R3 = (1.30 x 5.5)/(4.75 x 5E-6) = 301.05k. 301k is the nearest standard 0.1% value. Substitute into equation 2: R2 = [(1.30 x 5.5)/(4.4 x 5E-6)] - 301k = 23.95k. The nearest 0.1% resistor value is 23.7k. Finally, substitute into equation 3: R1 = (5.5/5E-6) - (23.7k + 301k) = 775k. The nearest 0.1% value resistor is 787k. Determine the actual low-line threshold by rearranging equation 1 and plugging in the standard resistor values. The actual lowline threshold is 4.75V and the actual reset threshold is 4.40V. An additional resistor allows the MAX792/MAX820 to monitor the unregulated supply and provide an NMI before the regulated supply begins to fall (Figure 4c). Both of these thresholds will vary from circuit to circuit with resistor tolerance, reference variation, and comparator offset variation. The initial thresholds for each circuit will also vary with temperature due to reference and offset drift. For highest accuracy, use the MAX820.
Monitoring the Regulated Supply
The MAX792/MAX820 offer two modes for monitoring the regulated supply and providing reset and nonmaskable interrupt (NMI) signals to the P: internal threshold mode uses the factory preset low-line and reset thresholds, and external programming mode allows the low-line and reset thresholds to be programmed externally using a resistor voltage divider (Figure 4). Internal Threshold Mode Connecting the reset-input/internal-mode select pin (RESET IN/INT) to ground selects internal threshold mode (Figure 4a). In this mode, the low-line and reset thresholds are factory preset by an internal voltage divider (Figure 1) to the threshold voltages specified in the Electrical Characteristics (Reset Threshold Voltage and Low-Line Threshold Voltage). Connect the low-line output (LOWLINE) to the P NMI pin, and connect the active-high reset output (RESET) or active-low reset output (RESET) to the P reset input pin. Additionally, the low-line input/reference-output pin (LLIN/REFOUT) connects to the internal 1.30V reference in internal threshold mode. Buffer LLIN/REFOUT with a high-impedance buffer to use it with external circuitry. In this mode, when VCC is falling, LOWLINE is guaranteed to be asserted prior to reset assertion.
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Microprocessor and Nonvolatile Memory Supervisory Circuits MAX792/MAX820
VCC 3
VCC RESET IN/ INT 4
2 RESET COMPARATOR RESET GENERATOR 1
RESET
*
RESET
VCC LLIN/ REFOUT 5 VCC LOW-LINE COMPARATOR VCC CHIP-ENABLE OUTPUT CONTROL MANUAL RESET COMPARATOR 1.30V VCC INTERNAL/ EXTERNAL MODE CONTROL VCC P 10 LOW LINE
MR
9
60mV INTERNAL EXTERNAL CE IN 14 TIMEBASE FOR RESET AND WATCHDOG 8 WATCHDOG TIMER WATCHDOG TRANSITION DETECTOR OVERVOLTAGE COMPARATOR OVI 7 N P 13 CE OUT
16 SWT 15
WDPO WDO
WDI
11 VCC
MAX792 MAX820
6 OVO
12 GND
* SWITCHES ARE SHOWN IN INTERNAL THRESHOLD MODE POSITION
Figure 1. MAX792/MAX820 Block Diagram _______________________________________________________________________________________ 9
Microprocessor and Nonvolatile Memory Supervisory Circuits MAX792/MAX820
VIN MR RESET 25s MIN 12s TYP 4 RESET IN/INT 3 VCC RESET 2 TO P
CE IN OV CE OUT 5 15s TYP
MAX792
LLIN/REFOUT RESET
1
TO P
LOW LINE
10
TO P NMI
Figure 2. Manual-Reset Timing Diagram
MANUAL RESET 9 * OTHER RESET SOURCES * . . . GND 12 MR
Figure 4a. Connection for Internal Threshold Mode MAX792 MAX820
R1 VIN
3 VCC RESET IN/INT RESET 2 TO P
* DIODES NOT REQUIRED ON OPEN-DRAIN OUTPUTS
Figure 3. Diode "OR" connections allow multiple reset sources to connect to MR.
R2
MAX792
LLIN/REFOUT RESET 1 TO P
Low-Line Output In internal threshold mode, the low-line comparator monitors VCC with a threshold voltage typically 120mV above the reset threshold, and with 15mV of hysteresis. For normal operation (VCC above the reset threshold), LOWLINE is pulled to VCC. Use LOWLINE to provide an NMI to the P, as described in the previous section, when VCC begins to fall (Figure 4).
R3 LOW LINE GND 12 R3 = 1.30V x VCC MAX VLOW LINE x IMAX R2 = 1.30V x VCC MAX - R3 VRESET x IMAX R1 = VCC MAX - (R2 + R3) IMAX
10
TO P NMI
IMAX = THE MAXIMUM DESIRED CURRENT THROUGH THE VOLTAGE DIVIDED.
Reset Function
The MAX792/MAX820 provide both RESET and RESET outputs. The RESET and RESET outputs ensure that the P powers up in a known state, and prevent code-execution errors during power-up, power-down, or brownout conditions. The reset function will be asserted during the following conditions: 1) VCC less than the programmed reset threshold. 2) MR less than 1.30V typ. 3) Reset remains asserted for 200ms typ after VCC rises above the reset threshold or after MR has exceeded 1.30V typ.
10
Figure 4b. Connection for External Threshold Programming Mode
When reset is asserted, all the internal counters are reset, the watchdog output (WDO) and watchdog-pulse output (WDPO) are set high, and the set watchdog-timeout input (SWT) is set to (VCC - 0.6V) if it is not already connected to V CC (for internal timeouts). The chipenable transmission gate is also disabled while reset is asserted; the chip-enable input (CE IN) becomes high impedance and the chip-enable output (CE OUT) is pulled up to VCC.
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Microprocessor and Nonvolatile Memory Supervisory Circuits MAX792/MAX820
REGULATOR 1 10k TO P RESET
RESET
R3 R1 R4
VCC RESET IN/INT RESET 2 TO P
MAX792 MAX820
MAX792 MAX820
LLIN/REFOUT RESET 1 TO P
R2 LOW LINE 10 VLOW LINE = 1.3 + ( R1R2R2 ) VRESET = 1.3 R3 + R4 ( R4 ) GND TO P NMI
Figure 5. Adding an external pull-down resistor ensures RESET is valid with VCC down to GND.
VOLTAGE REGULATOR
3 VCC
Figure 4c. Alternative Connection for External Programming Mode
Reset Outputs (RESET and RESET) The RESET output is active low and typically sinks 1.6mA at 0.1V. When deasserted, RESET sources 1.6mA at typically VCC - 1.5V. The RESET output is the inverse of RESET. RESET is guaranteed to be valid down to VCC = 1V, and an external 10k pull-down resistor on RESET ensures that it will be valid with V CC down to GND (Figure 5). As VCC goes below 1V, the gate drive to the RESET output switch reduces accordingly, increasing the rDS(ON) and the saturation voltage. The 10k pull-down resistor ensures that the parallel combination of switch plus resistor will be around 10k and the saturation voltage will be below 0.4V while sinking 40A. When using an external pull-down resistor of 10k, the high state for the RESET output with VCC = 4.75V is typically 4.60V.
7 OVI
MAX792 MAX820
OVO 6 OVERVOLTAGE
1.30V
GND 12
Figure 6. Detecting an Overvoltage Condition
Watchdog Function
The watchdog monitors P activity via the watchdog input (WDI). If the P becomes inactive, WDO and WDPO are asserted. To use the watchdog function, connect WDI to a P bus line or I/O line. If WDI remains high or low for longer than the watchdog timeout period (1.6s nominal), WDPO and WDO are asserted, indicating a software fault condition (see Watchdog-Pulse Output and Watchdog Output sections). Watchdog Input If the watchdog function is unused, connect WDI to VCC or GND. A change of state (high-to-low, low-to-high, or a minimum 100ns pulse) at WDI during the watchdog period resets the watchdog timer. The watchdog timer
11
Overvoltage Comparator
The overvoltage comparator is an uncommitted comparator that has no effect on the operation of other chip functions. Use this input to provide overvoltage indication by connecting a voltage divider from the input supply, as in Figure 6. Connect OVI to ground if the overvoltage function is not used. OVO goes low when OVI goes above 1.30V. With OVI below 1.30V, OVO is actively pulled to VCC and can source1A.
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Microprocessor and Nonvolatile Memory Supervisory Circuits MAX792/MAX820
1.6s WDI WDPO 70ns WDO MIN 100ns (VCC = 5V) MIN 300ns (VCC = 3V)
VCC 3 VCC 0.1F VCC P POWER 1 11 16 15 V CLOCK CC Q CLEAR Q TWO CONSECUTIVE WATCHDOG FAULT INDICATION RESET I/O
MAX792 MAX820
RESET WDI WDPO 9 MR GND 12 WDO
VCC = 5V
Figure 7. WDI, WDO, and WDPO Timing Diagram
+5V
D
*
default is 1.6s. Select alternative timeout periods by connecting an external capacitor from SWT to GND (see Selecting an Alternative Watchdog Timeout section). When VCC is below the reset threshold, the watchdog function is disabled. Watchdog Output WDO remains high if there is a transition or pulse at WDI during the watchdog timeout period. The watchdog function is disabled and WDO is a logic high when VCC is below the reset threshold. If a system reset is desired on every watchdog fault, simply diode-OR connect WDO to MR (Figure 8). When a watchdog fault occurs in this mode, WDO goes low, pulling MR low and causing a reset pulse to be issued. As soon as reset is asserted, the watchdog timer clears and WDO goes high. With WDO connected to MR, a continuous high or low on WDI will cause 200ms reset pulses to be issued every 1.6sec (SWT connected to V CC). When reset is not asserted, if no transition occurs at WDI during the watchdog timeout period, WDO goes low 70ns after the falling edge of WDPO and remains low until the next transition at WDI (Figure 7). A single additional flip-flop can force the system into a hardware shutdown if there are two successive watchdog faults (Figure 8). When the MAX792/MAX820 are operated from a 5V supply, WDO has a 2 x TTL output characteristic. Watchdog-Pulse Output As described in the preceding section, WDPO can be used as the clock input to an external D flip-flop. Upon the absence of a watchdog edge or pulse at WDI at the end of a watchdog timeout period, WDPO will pulse low for 1.7ms. The falling edge of WDPO precedes WDO by 70ns. Since WDO is high when WDPO goes low, the flipflop's Q output remains high after WDO goes low (Figure 8). If the watchdog timer is not reset by a transition at
12
0.1F REACTIVATE 4.7k * FOR SYSTEM RESET ON EVERY WATCHDOG FAULT, OMIT THE FLIP-FLOP, AND DIODE-OR CONNECT WDO TO MR.
Figure 8. Two consecutive watchdog faults latch the system in reset.
WDI, WDO remains low and the next WDPO following a second watchdog timeout period clocks a logic low to the Q output, pulling MR low and causing the MAX792/MAX820 latch in reset. If the watchdog timer is reset by a transition at WDI, WDO will go high and the flip-flop's Q output will remain high. Thus a system shutdown is only caused by two successive watchdog faults. Selecting an Alternative Watchdog Timeout Period The SWT input controls the watchdog timeout period. Connecting SWT to V CC selects the internal 1.6sec watchdog timeout period. Select an alternative watchdog timeout period by connecting a capacitor between SWT and GND. Do not leave SWT floating and do not connect it to ground. The following formula determines the watchdog timeout period: Watchdog Timeout Period = k x (capacitor value in nF)ms where k = 27 for VCC = 3V, and k = 16.2 for VCC = 5V. This applies for capacitor values in excess of 4.7nF. If the watchdog function is unused, connect SWT to VCC.
______________________________________________________________________________________
Microprocessor and Nonvolatile Memory Supervisory Circuits MAX792/MAX820
Chip-Enable Signal Gating
The MAX792/MAX820 provide internal gating of chipenable (CE) signals, which prevents erroneous data from corrupting CMOS RAM in the event of an undervoltage condition. The MAX792/MAX820 use a series transmission gate from CE IN to CE OUT (Figure 1). During normal operation (reset not asserted), the CE transmission gate is enabled and passes all CE transitions. When reset is asserted, this path becomes disabled, preventing erroneous data from corrupting the CMOS RAM. The 10ns max CE propagation delay from CE IN to CE OUT enables the MAX792/MAX820 to be used with most Ps. If CE IN is low when reset asserts, CE OUT remains low for a short period to permit completion of the current write cycle. Chip-Enable Input The CE transmission gate is disabled and CE IN is high impedance (disabled mode) while reset is asserted. During a power-down sequence when VCC passes the reset threshold, the CE transmission gate disables and CE IN immediately becomes high impedance if the voltage at CE IN is high. If CE IN is low when reset is asserted, the CE transmission gate will disable at the moment CE IN goes high or 15s after reset is asserted, whichever occurs first (Figure 9). This permits the current write cycle to complete during power-down. During a power-up sequence, the CE transmission gate remains disabled and CE IN remains high impedance regardless of CE IN activity, until reset is deasserted following the reset timeout period. While disabled, CE IN is high impedance. When the CE transmission gate is enabled, the impedance of CE IN will appear as a 75 (VCC = 5V) resistor in series with the load at CE OUT. The propagation delay through the CE transmission gate depends on VCC, the source impedance of the drive connected to CE IN, and the loading on CE OUT (see the Chip-Enable Propagation Delay vs. CE OUT Load Capacitance graph in the Typical Operating Characteristics). The CE propagation delay is production tested from the 50% point on CE IN to the 50% point on CE OUT using a 50 driver and 50pF of load capacitance (Figure 10). For minimum propagation delay, minimize the capacitive load at CE OUT, and use a low-output-impedance driver.
VCC RESET THRESHOLD CE IN
CE OUT
15s 70s
70s
RESET RESET
Figure 9. Reset and Chip-Enable Timing
+5V 3 VCC
14 50 DRIVER
MAX792 MAX820
CE IN CE OUT
13 CLOAD
GND 12
Figure 10. CE Propagation Delay Test Circuit
Chip-Enable Output When the CE transmission gate is enabled, the impedance of CE OUT is equivalent to 75 in series with the source driving CE IN. In the disabled mode, the 75 transmission gate is off and an active pull-up connects from CE OUT to VCC. This source turns off when the transmission gate is enabled.
Applications Information
Connect a 0.1F ceramic capacitor from VCC to GND, as close to the device pins as possible. This reduces the probability of resets due to high-frequency powersupply transients. In a high-noise environment, additional bypass capacitance from VCC to ground may be required. If long leads connect to the chip inputs, ensure that these lines are free from ringing, etc., which would forward bias the chip's protection diodes.
______________________________________________________________________________________
13
Microprocessor and Nonvolatile Memory Supervisory Circuits MAX792/MAX820
+5V 3 VCC RP* CE RAM 1 CE VCC CE 13 RAM 2 CE RESET CE GND 12 RAM 3 CE CE * MAXIMUM RP VALUE DEPENDS ON THE NUMBER OF RAMS. MINIMUM RP VALUE IS 1k RAM 4 CE ACTIVE-HIGH CE LINES FROM LOGIC GND 12 GND 3 VCC 1 4.7k RESET VCC P BUFFER TO OTHER SYSTEM RESET INPUTS
MAX792 MAX820
14 CE IN CE OUT
MAX792 MAX820
Figure 11. Alternate CE Gating
Figure 12. Interfacing to Ps with Bidirectional RESET Pins
Alternative Chip-Enable Gating
Using memory devices with both CE and CE inputs allows the MAX792/MAX820 CE propagation delay to be bypassed. To do this, connect CE IN to ground, pull up CE OUT to VCC, and connect CE OUT to the CE input of each memory device (Figure 11). The CE input of each memory device then connects directly to the chip-select logic, which does not have to be gated by the MAX792/MAX820.
Interfacing to Ps with Bidirectional Reset Inputs
Ps with bidirectional reset pins, such as the Motorola 68HC11 series, can contend with the MAX792/MAX820 RESET output. If, for example, the MAX792/MAX820 RESET output is asserted high and the P wants to pull it low, indeterminate logic levels may result. To avoid this, connect a 4.7k resistor between the MAX792/MAX820 RESET output and the P reset I/O, as in Figure 12. Buffer the MAX792/MAX820 RESET output to other system components.
going VCC pulses, starting at 5V and ending below the reset threshold by the magnitude indicated (resetcomparator overdrive). The graph shows the maximum pulse width a negative-going VCC transient may typically have without causing a reset pulse to be issued. As the amplitude of the transient increases (i.e., goes farther below the reset threshold), the maximum allowable pulse width decreases. Typically, a VCC transient that goes 100mV below the reset threshold and lasts for 30s or less will not cause a reset pulse to be issued. A 100nF bypass capacitor mounted close to the VCC pin provides additional transient immunity.
MAXIMUM TRANSIENT DURATION (s)
80
VCC = 5V TA = +25C
60
Negative-Going VCC Transients
While issuing resets to the P during power-up, powerdown, and brownout conditions, these supervisors are relatively immune to short-duration negative-going VCC transients (glitches). It is usually undesirable to reset the P when VCC experiences only small glitches. Figure 13 shows maximum transient duration vs. resetcomparator overdrive, for which reset pulses are not generated. The graph was produced using negative14
40
20 0 10 100 1000 10,000 RESET COMPARATOR OVERDRIVE, (VTH - VCC) (mV)
Figure 13. Maximum Transient Duration Without Causing a Reset Pulse vs. Reset-Comparator Overdrive
______________________________________________________________________________________
MAX791 -13
100
Microprocessor and Nonvolatile Memory Supervisory Circuits
_Ordering Information (continued)
PART** MAX792_EPE MAX792_ESE MAX792_EJE MAX792_MJE MAX820_CPE MAX820_CSE MAX820_EPE MAX820_ESE MAX820_EJE MAX820_MJE TEMP. RANGE -40C to +85C -40C to +85C -40C to +85C -55C to +125C -0C to +70C -0C to +70C -40C to +85C -40C to +85C -40C to +85C -55C to +125C PIN-PACKAGE 16 Plastic DIP 16 Narrow SO 16 CERDIP 16 CERDIP 16 Plastic DIP 16 Narrow SO 16 Plastic DIP 16 Narrow SO 16 CERDIP 16 CERDIP TOP VIEW
RESET 1 RESET 2 VCC 3 RESET IN/INT 4 LLIN/REFOUT 5 OVO 6 OVI 7 SWT 8 16 WDPO 15 WDO
Pin Configuration
MAX792/MAX820
MAX792 MAX820
14 CE IN 13 12 11 10 9 CE OUT GND WDI LOW LINE MR
* Dice are tested at TA = +25C, DC parameters only. **These parts offer a choice of five different reset threshold voltages. Select the letter corresponding to the desired nominal reset threshold voltage and insert it into the blank to complete the part number. Devices in PDIP, SO and MAX packages are available in both leaded and lead-free packaging. Specify lead free by adding the + symbol at the end of the part number when ordering. Lead free not available for CERDIP package. SUFFIX L M T S R RESET THRESHOLD (V) 4.62 4.37 3.06 2.91 2.61
DIP/SO
___________________Chip Topography
RESET RESET WDO CE IN
WDPO
V CC RESET IN/ INT LLIN/ REF OUT OVO
CE OUT
GND
0.078" (1.981mm)
WDI OVI SWT MR LOW LINE 0.070" (1.778mm)
TRANSISTOR COUNT: 950 SUBSTRATE CONNECTED TO VCC
______________________________________________________________________________________
15
Microprocessor and Nonvolatile Memory Supervisory Circuits MAX792/MAX820
________________________________________________________Package Information
INCHES
N
MILLIMETERS MIN 2.35 0.10 0.35 0.23 MAX 2.65 0.30 0.49 0.32
E
H
DIM A A1 B C e E H L
MAX MIN 0.093 0.104 0.004 0.012 0.014 0.019 0.013 0.009 0.050 0.299 0.291 0.394 0.419 0.016 0.050
1.27 7.40 7.60 10.00 10.65 0.40 1.27
1
VARIATIONS: INCHES MILLIMETERS MIN 10.10 11.35 12.60 15.20 17.70 MAX 10.50 11.75 13.00 15.60 18.10 N MS013 16 AA 18 AB 20 AC 24 AD 28 AE
TOP VIEW
D
DIM D D D D D
MIN 0.398 0.447 0.496 0.598 0.697
MAX 0.413 0.463 0.512 0.614 0.713
A e B A1
C 0-8 L
FRONT VIEW
SIDE VIEW
PROPRIETARY INFORMATION TITLE:
PACKAGE OUTLINE, .300" SOIC
APPROVAL DOCUMENT CONTROL NO. REV.
21-0042
B
1 1
INCHES DIM A A1 B C e E H L MAX MIN 0.069 0.053 0.010 0.004 0.014 0.019 0.007 0.010 0.050 BSC 0.150 0.157 0.228 0.244 0.016 0.050
MILLIMETERS MAX MIN 1.35 1.75 0.10 0.25 0.35 0.49 0.19 0.25 1.27 BSC 3.80 4.00 5.80 6.20 0.40 1.27
N
E
H
VARIATIONS:
1
INCHES
MILLIMETERS MIN 4.80 8.55 9.80 MAX 5.00 8.75 10.00 N MS012 8 AA 14 AB 16 AC
TOP VIEW
DIM D D D
MIN 0.189 0.337 0.386
MAX 0.197 0.344 0.394
D A e B A1 L C
0-8
FRONT VIEW
SIDE VIEW
PROPRIETARY INFORMATION TITLE:
PACKAGE OUTLINE, .150" SOIC
APPROVAL DOCUMENT CONTROL NO. REV.
21-0041
B
1 1
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
16 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2005 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products, Inc.
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